$\begin{array}{|l|l|l|}
\hline \mathrm{A} & \mathrm{B} & \mathrm{Y} \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 0 \\
\hline 1 & 0 & 1 \\
\hline 1 & 1 & 1 \\
\hline
\end{array}$To obtain the truth-table shown, from the following logic circuit, the gate $\mathrm{G}$ should be…
$\begin{array}{|l|l|l|}
\hline \mathrm{A} & \mathrm{B} & \mathrm{Y} \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 0 \\
\hline 1 & 0 & 1 \\
\hline 1 & 1 & 1 \\
\hline
\end{array}$- AND
- NAND
- OR
- NOR
Solution
The truth table for given configuration is as shown below.
$\begin{array}{|c|c|c|c|c|}
\hline \text{Case} & \mathbf{A} & \mathbf{B} & \mathbf{C} & \mathbf{A}+\mathbf{C}=\mathrm{Y} \\
\hline \text{I} & 0 & 0 & \mathrm{C}_1 & 0+\mathrm{C}_1=1 \\
\hline \text{II} & 0 & 1 & \mathrm{C}_2 & 0+\mathrm{C}_2=0 \\
\hline \text{III} & 1 & 0 & \mathrm{C}_3 & 1+\mathrm{C}_3=1 \\
\hline \text{IV} & 1 & 1 & \mathrm{C}_4 & 1+\mathrm{C}_4=1 \\
\hline
\end{array}$
Considering case (I), in order to have output $\mathrm{Y}$ as $1$, $\mathrm{C}_1$ has to be $1$. For input values, $\mathrm{A}=0$ and $\mathrm{B}=0$, if $\mathrm{C}_1$ is to be high, the gate $\mathrm{G}$ could be either NAND or NOR.
Considering case (II), in order to have output $\mathrm{Y}$ as $0$, $\mathrm{C}_2$ has to be $0$. For input values, $\mathrm{A}=0$ and $\mathrm{B}=1$, if $\mathrm{C}_2$ is to be $0$, the gate must be NOR.Asked in: MHT CET 2023 (10 May Shift 1)