The logic circuit in figure is equivalent to

The logic circuit in figure is equivalent to
  1. OR gate
  2. AND gate
  3. NOR gate
  4. NAND gate

Solution

The output of the NAND gate will be $\overline{\mathrm{A} \cdot \mathrm{B}}$. The output of the NOR gate will be $\overline{\overline{\bar{A} \cdot \mathrm{~B}}+\overline{\overline{\mathrm{A} \cdot \mathrm{~B}}}}=\mathrm{A} \cdot \mathrm{~B}$
The output of the NOT gate will be $\overline{\mathrm{A} \cdot \mathrm{B}}$ Thus, the given network is equivalent to a NAND gate.

Asked in: MHT CET 2024 (02 May Shift 1)

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