The truth table of the given circuit diagram is :

From the diagram, it is clear that the first set of gates are NOT gates, the second set of gates are AND gates and the third and final gate is an OR gate.

The final output from all the combination of the gates can be written as

$\mathrm{Y}=\mathrm{A}·\overline{\mathrm{B}}+\overline{\mathrm{A}}·\mathrm{B}$

This indicates a XOR GATE. Hence, this option indicates the correct truth table.