The logic performed by the circuit shown in figure is equivalent to

All the gates used in the given configuration are $\mathrm{NOR}$ gates. Thus, the output can be found as follows-

$\begin{array}{rcl}Y& =& \overline{\left(\overline{a}+\overline{b}\right)}\\ & =& \overline{\left(\overline{ab}\right)}\\ & =& ab\end{array}$

The output of the given configuration can also be verified by the following truth table:

The calculation and the truth table clearly shows that the configuration represents $\mathrm{AND}$ gate.