In the given circuit the input voltage V in   is shown in figure. The cut-in voltage of p - n junction…

During the positive half cycle of the input waveform, diode $D_1$ is forward biased and diode $D_2$ is reverse biased. Here $0.6 \mathrm{V}$ appears across the output as the diode is conducting. During negative half cycle the diode $D_1$ is reverse biased and $D_2$ is forward biased, so, $-0.6 \mathrm{V}$ appears across the output as the diode is conducting in negative direction. This circuit can be used as a voltage limiter. This circuit will not allow any voltage above $0.6 \mathrm{V}$and below $-0.6 \mathrm{V}$.

Hence, the output waveform is